The present invention relates to a semiconductor device and relates to an effective technology applicable to a semiconductor device including a power source circuit driving a circuit operating at a high speed.
For example, Japanese Unexamined Patent Application Publication No. 2011-165858 discloses a semiconductor device in which a semiconductor chip mounted on a wiring substrate are electrically coupled to the wiring substrate through a plurality of wires. Japanese Unexamined Patent Application Publication No. 2011-165858 discloses that parasitic inductance can be reduced by arranging, in plan view, a plurality of power source pads for supplying a power source between comb-shaped ground pads for supplying a ground voltage.